Memory control circuit

ABSTRACT

A dynamic memory circuit in which the stored information is periodically refreshed includes a circuit for precharging the write digit lines of the memory circuit when an access signal is received from an external source. The precharge circuit includes circuit means which prevent the precharge of the write digit lines in response to an access signal while any of the write gates of the memory cells of the circuit are closed to prevent the destruction of the information stored in the memory cells.

United States Patent [191 Matsue Aug. 27, 1974 MEMORY CONTROL CIRCUIT3,790,961 2/1974 Palfi 340/173 DR [75] Inventor: Shigeki Matsue, Tokyo,Japan P E T n w F rlmary xammererre ears [73] Assignee: Nippon ElectricCompany Limited, Attorney Agent or p s Hopgood &

Tokyo, Japan Calimafde [22] Filed: Sept. 18, 1973 [21] Appl. No.2398,340 ABSTRACT A dynamic memory circuit in which the stored infor- 30Foreign Application p i Data mation is periodically refreshed includes acircuit for Se t 19 1972 Ja an 4794370 prechargmg the write digit linesof the memory circult p when an access signal is received from anexternal source. The precharge circuit includes circuit means g 340/173bfiS I which prevent the precharge of the write digit lines in [58] d DR172 5 response to an access signal while any of the write e o gates ofthe memory cells of the circuit are closed to [56] References Citedprevent the destruction of the information stored in UNITED STATESPATENTS 7/l973 Mesnik 340/173 DR the memory cells.

5 Claims, 7 Drawing Figures PAIENI msz 1 I974 3.832.699 SIIEEHIIF 3"MEMORY CONTROL CIRCUIT BACKGROUND OF THE INVENTION The present inventionrelates to a dynamic memory circuit employing insulated-gate fieldeffect transistors (hereinafter referred to as IGFETs), and particularlyto such a circuit having protection against the destruction of theinformation stored in the memory circuit.

In general, a memory cell of a dynamic memory circuit includes acapacitor for storing information in the form of electric charges, awrite gate for putting (or writing) information in the form of electriccharges into the capacitor, and a read gate for taking out (or reading)information in the form of electric charges from the capacitor. In sucha'memory cell, the stored information will be lost gradually with alapse of time because of leakage of electric charges from thecapaciperiodically. The dynamic memory circuit must therefore beoperated with an extra cycle time for refreshing the electric charges onthe capacitors in addition to the normal cycle time which is used forexternally writing and reading information into and out of thecapacitors of the respective memory cells.

In order to ensure high speed operation of the dynamic memory circuit,the memory circuit is often used in such a manner that access signalsfrom an external source such as a central processing unit (CPU) areasynchronously supplied to the memory circuit and the refreshing cycleis executed asynchronously with the operation of the CPU during theperiod when no access signal is present from CPU. In such a system, anaccess signal may come to the memory circuit during the refreshingcycle, causing information to be read from or written into the memorycircuit by the external source such as a CPU. To reduce the timenecessary for preforming such an external read/write operation, it isnecessary to interrupt the refreshing cycle and to execute the externalread/write operation immediately. There is a possibility that theinformation stored inthe cell will be destroyed by the interruption ofthe refreshing cycle during certain periods.

. The refreshing cycle of the dynamic memory circuit begins with theprecharging of a read digit line (RDL) which is connected to the readgate of the memory cell and a write digit line (WDL) which is connectedto the write gate of the cell. After the precharge, the read gate isclosed by a signal supplied by a read address line (RAL) causing thetransfer of the information stored in the capacitor of the memory cellto the precharged RDL. The information is then transferred from RDL, tothe WDL. Thereafter, the write gate of the cell is closed by a signalthrough a write address line (WAL) causing the information on the WDL tobe transfered back to the capacitor of the memory cell. In this way theinformation stored in the capacitor is refreshed during each refreshingcycle. When the memory circuit receives an access signal from the CPU,the refreshing cycle is interrupted, and the memory cycle immediatelybegins an external read/write operation with the precharge of the WDLand the RDL. However, if the refreshing cycle is interrupted at a timewhen the write gate is closed, it may occur that the precharge voltageon the WDL rather than the information transferred to WDL will bewritten into the capacitor of the memory cell through the closed writegate. This can occur betor. Therefore, the capacitor charge must berefreshed cause the precharge of the WDL starts immediately. If thisoccurs the stored information in the memory cell will not be refreshedand will in fact be destroyed. Such destruction of the storedinformation can also occur in a dynamic memory circuit wherein the RDLis omitted and the read gate of the memory cell is connected to WDL.

Therefore, an object of this invention is to provide a dynamic memorycircuit in which the stored information is protected against destructionbased on the interruption of the refreshing cycle.

BRIEF DESCRIPTION OF THE INVENTION According to this invention, adynamic memory circuit is provided with means for generating a prechargesignal commanding the precharge of the write digit line, said generatingmeans including means to prevent the generation of said precharge signaluntil after the write gates of the memory cells which are connected tothe write digit line are opened. In a first embodiment of the inventionsuch generating means responds to a signal on the write address lineindicating the closing of the write gates and delays the prechargecommand signal until after the signal indicating the closing of thewrite gates has disappeared from the write address line. Such agenerating means comprises a NOR circuit having its input terminalsconnected to the write address lines of a memory matrix. The NOR circuitgenerates an output signal only when no write gate closing signal ispresent on any write address line. This output of the NOR circuit can beused as a signal commanding the precharge of all the write digit linesof the memory matrix. Another example of the generating means mayincludes a delay circuit which provides a delay signal to close a gatewhich connects a write address line to the ground. The delay circuit canbe used with an inverter circuit which inverts a timing signal to makethe write address line active. The delayed signal or the inverted timingsignal can be used as the precharge command signal.

According to this invention, a signal commanding the precharge of thewrite digit lines is always generated when no signal is present on theaddress lines so that the write gates of memory cells are opened. Inother words, the write digit lines are not precharged until the writegates are opened so that the stored information in the memory cells isfully protected against destruction, even when the refreshing cycle isinterrupted due to an access from the CPU.

The invention will be described more in detail, with reference to theaccompanying drawings in which FIG. 1 is a diagram of a memory circuitaccording to the first embodiment of this invention;

FIG. 2 shows waveforms to illustrate the operation of the memory circuitshown in FIG. 1;

FIG. 3 is a diagram example of an inverter circuit which may beincorporated in the memory circuit of the invention;

FIG. 4 is a diagram of another example of a dynamic memory cell which isusable in the memory circuit of the invention; and

FIGS. 5, 6 and 7 are diagrams of alternate embodiments of a circuit forgenerating a signal commanding the precharge of the write digit lines ofthe memory matrix according to the invention.

The description of the invention in this specification will be based onthe assumption that IGFETs em- 4 known to those skilled in the art thefunctions of the circuits described would be essentially identical if P-channel type IGFETs are employed so that the present invention can beapplied to memory circuits employing any kinds of lGFETs. Although amemory circuit of 64 bits will be described below as an example, thepresent invention can be similarly applied to memory circuits of anarbitrary'number of bits.

Referring to FIG. 1, a memory circuit of 64 bits receives six addresssignals X, to X supplied from outside the circuit. Each of the firstthree input address signals X X and X is applied respectively to anaddress buffer l-l, 1-2, and 1-3 and each buffer produces amplified trueand complementary signal (X X (X X (X X corresponding to each addresssignal. The buffer output signals are applied to decoders 2-1 2-8 whichconsist of 3-input NOR circuits. The outputs D D of the decoders 2-1 2-8are used for selection of the 64 memory cells 4-11 4-88 which arearranged to form a matrix 5 consisting of eight lines and eight columns.The selection of the 64 bits is divided into two parts. The selection ofthe first eight words in the memory matrix 5 is performed by using thetrue and complementary signals of the three address signals X, to X;,which are applied respectively to eight address decoders 2-1 to 2-8. Theoutput Di of the selected decoder 2-i (i represents 1,2, or 8) issubjected to power amplification to providehigh speed operation byanother switch 3-i and is then applied to a selected pair of read andwrite address lines RAL-i and WAL-i. The memory cells 4-i1 to 4-i8 ofthe eight bits connected to the selected address line pair aresimultaneously subjected to either a read signal causing the storedinformation in the memory cells to be readout by read digit lines RDL-Ito RDL-8 or to a write signal causing information from the write digitlines WDL-l to WDL-8.

The selection among the eight bits in the memory matrix 5 is carried outby processing the remaining three address signals X, to X in a bitselect line driver 6 which includes address buffers, decoders andswitches similar to those described above and in which the selecteddigit lines WDL-j (1' being 1,2, or 8) of the memory matrix 5 isconnected to the terminals data IN and data OUT. By this arrangement,only one information bit is selected and read out from the informationcontained in the eight bits which are connected to a selected addressline pair and which have all been simultaneously read out to the writedigit lines WDL-l to WDL-8.

In the write operation, data supplied from an external source to the INterminal is written, through the selected digit line WDL-j, into theonly one'selected bit 4-ij where the selected address lines cross theselected digit lines. As for the remaining seven unselected bits of theselected address line, the data of the bits which is read out to theread digit lines (RDL) and is transmitted to the write digit lines (WDL)by data transmission circuits consisting of IGFETs Q, and Q and is thenrewritten into the unselected bits of the selected address line.

These operations of the memory circuit of FIG. 1 are effected notconcurrently but successively in time, and v the sequence and mutualrelation in time of the operations are determined by timing or commandsignals to $5 and auxiliary timing signals P0 to P2 as shown in FIG. 2.

When the timing signal $0 is supplied to the address buffers 1-1 through1-3, the inverter transistors 0, and Q in each buffer operate togenerate true and complementary signals responsive respectively to inputaddress signals X, to X, appear at points Al and A2 of the buffers 1-1to l-3. Prior to the signal $0, a timing signal Po, which had clampedthe voltage of points Al and A2 at a low level falls unclamping pointsA1 and A2. As soon as the levels of Al and A2 have been determined, asX, and X, respectively the next timing signal $1 is applied to thetransistors Q and Q A period T1 is the time required for determining thelevels of the true and complementary signals X X, at the points A1 andA2 of the address buffers l-l to 1-3. Upon the application of signal $1,the signals X, X, at the points Al, A2 in the address buffers l1 to 1-3are transmitted through the switches O O to the inputs of the decoders2-1 to2-8. Before the application of signal $1,

.a timing signal P1 had clamped the outputs D through D of each decorderat 2-1 through 2-8 high level P, then falls down into the unselectedbits of the selected address line. The output Di, of the selecteddecoder 2-i, which has all input signals at the low level is at the highlevel. The outputs of all the other decoders, in which at least oneinput is at the high level, fall to the low level. A period T2 is thetime required for determining the level of the decoder outputs D afterthe application of the signal $1.

Then, the signal $2 is then applied to the switches 3-1 to 3-8. Theoutputs Di of the selected address decoder 2-i being high turns thecorresponding read address line RAL-i to the high level. Prior to thisall the read address lines have been clamped at the low level by signal2 and, the non-selected read address lines remain at the low level.Before signal $2, is applied the Signal P2 falls to the low level. WhenP2 was high it had closed transistors 0 and Q connecting the read andwrite digit lines RDL, and WDL to the power source VDD, respectively,and had caused all the digit lines RDL, WDL to be precharged at the highlevel of the power source. With the selected read address line RAL-iturned to the high level a, read operation of the memory cells 4-i1 to4-i8 which are connected to RAL-i is initiated. In detail, the gate of aread gate transistor Q, is connected to the selected high level readaddress line RAL-i so that Q, is turned on and the data stored in thecapacitance C at a point M of each memory cell (see cell 4-11 forexample) is read out to each read digit line RDL. If the capacitor C isnot charged and the point M is at the low level, an amplifyingtransistor 0 is biased off and the read digit line RDL of that memorycell will remain at the high level, whereas if the capacitor C ischarged and the point M is at the high level, the transistor Q thetransistor will be biased on and the RDL will fall to the low level bybeing connected to the ground through the transistors Q and O in thememory cell. A period of time T3 is required from the application ofsignal $2 to the determination of the level of the read digit linesRDL-1 through RDL-8.

Upon the application of signal $3, the data transmission transistors Q;are switched on causing the level of each write digit line WDL to bedetermined by the level of the corresponding read digit line RDL. If theRDL is at the low level, the WDL will remain-atthe high level to whichit has been raised by P2. On the other hand, if RDL is at the high level0., is switched on and, WDL is grounded through 0,, and Q and the levelof WDL will fall to the low level. A period T4 is the time which isnecessary to determine the level of WDL, or to perform the datatransmission from the read digit lines to the write digit lines afterthe application of signal (233.

When signal O4 is applied to the switches 3-1 to 3-8, the high level ofthe output Di of the selected address decoder 2-i is transmitted to thecorresponding write address line WAL-i by the transistor Q14 of theswitch 3-i. With the write address line WAL-i thus turned to the highlevel, the write gate transistor Q of the memory cells 4-il to 4-8 turnson and the data having been transmitted to the write digit lines WDL-lto WDL-8 to the point M of the respective memory cells which areconnected with this write address line through Q This is the rewriteoperation of the stored data, because the data having been transmittedto WDL is in conformity with the stored data of the memory cells and isrewritten in the cells. A period T5 is the time necessary for therewrite operation. I

For writing new data into a memory cell from an external source, atiming signal (55 is applied to the write digit lines WDL-l to WDL-8.When the signal (Z55 becomes high in level, all the write digit linesare prepared to be connected to the data IN terminal but only theselected write digit line WDL-j which has been already connected by theaddress signals X through X is able to receive new information from theexternal source and the information is written into the selected memorycell 4-ij which is connected to both the selected address lines anddigit lines. A period T6 is a time required for a new information to betransmitted from the external source through the write digit line to thepoint M of the selected memory cell. The read operation of the storeddata from the selected write digit line to the data OUT terminal is alsoperformed in this period T6 by using signal Q5.

The refreshing operation will now be explained more in detail, withreference to FIGS. 1 and 2. Assuming that the capacitor C of the memorycell 4-11 is not charged so that the stored information in this cell isO. The signal P which commands the precharge of the digit lines WDL, andRDL drops to the low level, and then the timing signal Q5 causes thelevel of RAL to rise as shown in FIG. 2. Since the stored information is0, the level of RDL remains high. Then the timing signal (2);, is thenapplied to the transmission transistor Q causing WDL to to drop the lowlevel. Thereafter, the timing signal G is applied through the transistorO of the switch 3-l 'to the write address line WAL, which has beenmaintained at the low level because transistor 0 was closed by anaddress reset signal AR (in this case, O unclamping the decoder outputs.WAL, then rises to the high level and closes the write gate 0 of thememory cell 4-11. This permits charges which may have accumulated on thecapacitor C to be discharged through Q, and WDL,, and thus theinformation 0 is rewritten at the point M. Following the change of thesignal (D to the low level, all the timing signals (2), to (2),, fall tothe low level and then signals P .to P start to rise. However, if thesignal P starts to rise because of the interruption of the refreshingcycle at a time point when WAL, has not yet returned to the low level,charges from the power supply V will flow through the closed prechargegate 0 WDL, and the closed write gate O to charge the capacitor C andthereby destroy the stored information 0. In order to prevent suchdestruction, the precharge command signal P should rise only after thetiming signal (25., falls, causing the address reset signal AR to riseand the write address line WAL to fall to the low level.

Referring further to FIG. 1, this invention provides a circuit 7 forgenerating the precharge command signal P This circuit 7 comprises a NORcircuit formed by switching transistors Q to Q which are connected inparallel with each other between, output point and ground and a loadtransistor Q which is connected between the output point 70 of the NORcircuit and the power supply V Each gate electrode of the switchingtransistors Q to Q which is an input terminal of the NOR circuit, isconnected respectively to one of the write address lines WAL, to WAL Aninverter 71 is connected to the gate electrode of the load transistor Qand the timing signal (D is applied to the imput of this inverter 71 toprovide an output 6 The output point 70 of the NOR circuit is connectedthrough two stages of inverters 72 and 73 to an output terminal 74 whichis in turn connected to the gate electrodes of the transistors Q and Qwhich control the precharge the digit lines'WDL and RDL.

In this circuit 7, the output point 70 will be at the low level if anyof the write address lines WAL to WAL is at the high level indicating aclosed write gate. The output point 70 will become high only when allthe write address lines WAL to WAL are at the low level and an invertedtiming signal 6 has risen to the high level closing Q The two stages ofinverters 72 and 73 serve to amplify the output signal present at point70 and to delay the output signal slightly to ensure circuit operation.Thus, a precharge command signal P is generated at the output terminal74 and this signal P becomes high only after all the write address linesare at the low level indicating that the write gates are closed, even ifthe cycle is terminated in any manner.

The gate electrode of the load transistor Q may be connected to thepower source V with the inverter 71 omitted. Moreover, the prechargecommand signal P may be taken from the output point 70 omittinginverters 72 and 73. Any known inverter circuit can be used forinverters 71 through 73. FIG. 3 shows an example of a usable knowninverter circuit, which comprises a switching transistor Q and a loadtransistor Q Input and output terminals 75 and 76 of this inverter arethe gate and drain electrodes of the switching transistor Qrespectively.

In the memory circuit of the invention, a memory cell such as that shownin FIG. 4 can be employed instead of the memory cell 4ij of FIG. 1. Insuch cell, the information stored in a capacitor C is read out through aread gate transistor 0;, to a write digit line WDL and the informationis rewritten into the cell through a write gate transistor Q to thecapacitor C. Therefore, the problem to be solved with this memory cellis the same as in the case of using the memory cell 4ij of FIG. 1.

Referring to FIG. 5, another example of a circuit for generating thepercharge command signal P comprises an inverter 77 and a delay circuitconnected in sew ries to the output of the inverter 77.The timing signalQ5 is ap lied to the input of the inverter 77 to provide output When thetiming signal becomes low, the

address reset signal AR which is the output 6 of inverter 77 becomeshigh. The signal AR turns gate Q on providing a path to ground for thewrite address lines. The delay circuit 85 delays the signal AR for atime period which is long enough to insure that the write address lineshave fallen to the low level in response to AR having turned to the highlevel. Thus, the signal P is generated as a delayed signal from theaddress reset signal AR.

FIG. 6 illustrates still another embodiment of the invention whichcomprises a series connection of an inverter 78, a two-input NOR circuit86 and a second inverter 79. The input of inverter 78 is timing signaland the inverter 78 produces an output which serves as address resetsignal (AR). Signal AR is applied to one input of NOR circuit 86 and asignal commanding the generation of signal (6., is applied to the secondinput of the NOR circuit 86. After AR reaches the high level, the signal(D which is the output of NOR circuit 86, becomes low. Low signal ispassed through inverter 79 to provide P as its output which is then atthe high level. The NOR circuit 86 and the inverter 79 perform thefunction of the delay circuit 85 of FIG. 5.

FIG. 7 shows a further embodiment of the invention which comprises twostages of series connected inverters 80 and 81 which receive input (23 atwo input NOR circuit 86' recieving as its inputs the output of thesecond inverter 81 and a signal commanding the generation of timingsignal Q3 so that the output of the NOR circu i t 86 is An inverter 82receives (2)., and generates (1, which serves as an address reset signalwhich is applied to two stages of inverters 83 and 84. The output of thesecond inverter 84 serves as signal P In this circuit, Q), is initiallyat a low level causing AR to be high, and P is generated by delayinghigh signal AR with two inverters 83 and 84.

In the circuits of FIGS. 5, 6 and 7, a known inverter circuit such asshown in FIG. 3 can be employed as the inverters 77 to 84.

It will be evident that the invention is applicable to any dynamicmemory circuit where refreshing is needed including such circuitsemploying bipolar transistors.

What is claimed is:

l. A dynamic memory circuit including:

a plurality of memory cells each of said memory cells including a writegate and information storage means connected to said write gate,

means for periodically refreshing the information stored in saidinformation storage means,

at least one write digit line connected to a number of said write gatessaid write digit line being adapted to provide voltage to write saidinformation into said information storage means when said write gate isclosed,

means for providing a timing signal,

generating'means responsive to said timing signal to generate aprecharge signal causing said write digit line to be precharged to apredetermined voltage condition,

said generating means being adapted to prevent the generation of saidprecharge signal while any of said write gates are closed.

2. A dynamic memory circuit as claimed in claim 1, wherein saidgenerating means includes at least one write address line, said writeaddress line being connected to said write gates and the voltage on saidwrite address line being representative of the closed condition of anyof said write gates, and a NOR circuit connected in series between avoltage source and said at least one write digit line, said at least onewrite address line being connected to an input of said NOR circuit theoutput of said NOR circuit being said precharge signal.

3. A dynamic memory circuit as claimed in claim 2 including delay meansconnected between the output of said NOR circuit and said write digitlines.

4. A dynamic memory circuit as claimed in claim 1, wherein saidgenerating means includes means to generate a reset signal in responseto said timing signal, means responsive to said reset signal to opensaid write gates, a delay circuit having a delay period long enough topermit the open of said write gates by said reset signal, said resetsignal 65 being connected to theinput of said delay circuit and theoutput of said delay circuit providing said precharge signal.

5. A dynamic memory circuit as claimed in claim 4, wherein said delaycircuit includes a two input NOR circuit series connected to an invertercircuit.

I UNIT D STATES ATENT OFFICE CERTIFICATE OF CQRRECTION Patent No.3,832,699 ate August 27, 1974 Inventor(s) MATSUE, Shigeki It iscertified that error appears in the above-identified patent and thatsaid: Letters Patent are hereby corrected-as shown below:

Claim Column 8, Line 38 the word o en should be ogening Q Claim 4.COlImm 8, Line 39 the number should be deleted 1 Signed and sealed-this3rd day of December 1974.

(SEAL)- Attestz' McCOY M. GIBSON JR. .c. MARSHALL DANN Attesting Officerr Commissioner of Patents

1. A dynamic memory circuit including: a plurality of memory cells eachof said memory cells including a write gate and information storagemeans connected to said write gate, means for periodically refreshingthe information stored in said information storage means, at least onewrite digit line connected to a number of said write gates said writedigit line being adapted to provide voltage to write said informationinto said information storage means when said write gate is closed,means for providing a timing signal, generating means responsive to saidtiming signal to generate a precharge signal causing said write digitline to be precharged to a predetermined voltage condition, saidgenerating means being adapted to prevent the generation of saidprecharge signal while any of said write gates are closed.
 2. A dynamicmemory circuit as claimed in claim 1, wherein said generating meansincludes at least one write address line, said write address line beingconnected to said write gates and the voltage on said write address linebeing representative of the closed condition of any of said write gates,and a NOR circuit connected in series between a voltage source and saidat least one write digit line, said at least one write address linebeing connected to an input of said NOR circuit the output of said NORcircuit being said precharge signal.
 3. A dynamic memory circuit asclaimed in claim 2 including delay means connected between the output ofsaid NOR circuit and said write digit lines.
 4. A dynamic memory circuitas claimed in claim 1, wherein said generating means includes means togenerate a reset signal in response to said timing signal, meansresponsive to said reset signal to open said write gates, a delaycircuit having a delay period long enough to permit the open of saidwrite gates by said reset signal, said reset signal 65 being connectedto the input of said delay circuit and the output of said delay circuitproviding said precharge signal.
 5. A dynamic memory circuit as claimedin claim 4, wherein said delay circuit includes a two input NOR circuitseries connected to an inverter circuit.